A multi-core processor is a central processing unit (CPU) formed by integrating multiple processor cores on a single processor chip. An independent-entity central processing unit is also referred to as a processor core, a kernel, or a core and is the most important constituent part of the CPU. The processor core performs all computation, command receiving/storage, and data processing of the CPU. Each type of CPU processor core has a fixed logical structure that includes a level 1 cache, a level 2 cache, an execution unit, an instruction-level unit, a bus interface, and the like.
A processor is a core part of a computer system. As an application program has an ever-increasing requirement for a capability of processing high-throughput data, a conventional solution for improving performance of a single-core processor is limited by an integration level, power consumption, and a delay. Currently, an on-chip multi-core solution of replacing a single complex core with multiple simple cores is generally used in the industry. A physical memory needs to be shared by multiple processor cores, and each processor core has its own private cache. Therefore, when accessing the shared physical memory, a processor core generally needs to copy a data block from the shared physical memory to its own private cache, so as to accelerate data access. When multiple processor cores access the shared physical memory, a copy of the data block in the shared physical memory exists in private caches of the multiple processor cores. Therefore, a cache coherence protocol is required to manage data sharing, so as to maintain coherence of the copies. When performing a write operation on a shared data block or a copy of the shared data block, a processor core may send a write invalidate operation or a write update operation to a processor core that stores a copy of the shared data block, so as to avoid a data incoherence problem. Cache coherence may be maintained by recording a cache status of a data block (or a data block interval). The cache status of the data block (or the data block interval) may include an access type and a sharer of the data block (or the data block interval).
Currently, there are mainly two cache coherence protocols: a bus-snooping based coherence protocol, and a directory structure-based coherence protocol. In the directory structure-based coherence protocol, a fetch demand of a single processor core is first sent to a directory structure that has an accessed cache block, and the directory structure records a sharing status of the cache block. A write invalidate operation or a write update operation is sent to only a processor core recorded in the directory structure, thereby avoiding unnecessary bandwidth overheads. For the directory structure-based coherence protocol, because the directory structure also occupies on-chip storage space, important research content is to reduce storage overheads of the directory structure.
In a prior art of the present disclosure, data blocks of a specific quantity are grouped into several data block intervals. Each data block interval includes multiple data blocks, a shared interval directory entry is used to indicate a cache status of the data block interval, and one or more line directory entries are used as a supplementary. One line directory entry in an interval directory entry is corresponding to one data block in a data block interval corresponding to the interval directory entry, and is used to indicate a cache status of the data block. A cache status of the line directory entry is different from a cache status of the interval directory entry. If a write operation is frequently performed on multiple data blocks in an interval, multiple line directory entries are generated, which leads to an extremely large total quantity of directory entries, such that storage overheads occupied by the directory entries cannot be reduced.
In another prior art of the present disclosure, data blocks of a specific quantity are grouped into several data block intervals. Each data block interval includes multiple data blocks, a private interval directory entry is used to indicate a cache status of the data block interval, and one or more line directory entries are used as a supplementary. One line directory entry in an interval directory entry is corresponding to one data block in a data block interval corresponding to the interval directory entry, and is used to indicate a cache status of the data block. A cache status of the line directory entry is different from a cache status of the interval directory entry. If another processor node frequently performs a read or write operation on multiple data blocks in an interval, multiple line directory entries are generated, which also increases a total quantity of directory entries and storage overheads of the directory entries.
A technical solution is required to correctly indicate a sharing status of a data block and improve utilization of on-chip storage space of a directory.